Applications of Low-Temperature Flow-able Chemically Vapor Deposited Borophosphosilicate Glass Thin Films in Integrated and Microsystem Technologies—An Overview of Current Status

Integrated circuit (IC) technology has become the foundation and driving force behind the advancement of integrated technologies in modern electronic devices. ICs are fabricated on monocrystalline silicon substrates with defined conductivity and crystallographic orientation, typically ranging from several inches in diameter and several hundred microns in thickness. Over the past 60 years, IC technology has undergone continuous development, commonly described by Moore’s Law [1], with feature sizes reduced from tens of micrometers to the nanometer scale [2]. This progress has been enabled by advances in material systems, fabrication processes, production equipment, and process control.

Since the 1970s, stoichiometric silicon dioxide (SiO$_2$) has been widely used as a dielectric material in IC technologies. Due to its compatibility with silicon substrates, SiO$_2$ serves as an insulating material both within the substrate and in the form of thin films deposited on its surface. These thin films, typically with thicknesses up to the micrometer scale, are commonly produced using chemical vapor deposition (CVD) processes, such as the oxidation of silane (SiH$_4$) or tetraethylorthosilicate (TEOS, Si(OC$_2$H$_5$)$_4$). In such processes, a solid thin film is formed on a heated substrate through chemical reactions involving gaseous precursors. The growth of these films depends on multiple parameters, including temperature, pressure, precursor concentration, gas flow rate, and deposition time. As a result, silicon dioxide thin films remain an essential component of IC manufacturing.

It was subsequently observed that SiO$_2$-based dielectric materials containing additives such as phosphorus, boron, germanium, and arsenic oxides exhibit properties that are advantageous for IC fabrication. The incorporation of these oxides reduces the glass transition temperature (T$_{\text{g}}$), enabling softening and flow at temperatures significantly lower than the melting point of pure SiO$_2$. Among these materials, phosphosilicate glass (PSG, SiO$_2$–P$_2$O$_5$) and borophosphosilicate glass (BPSG, SiO$_2$–B$_2$O$_3$–P$_2$O$_5$) have been extensively utilized, with the total additive content typically limited to approximately 30 wt % (corresponding to about 12–15 wt % elemental content). For PSG, T$_{\text{g}}$ decreases from approximately 1150 ℃ to 730 ℃ as the phosphorus content increases from 0 to 8 wt % [3]. These modified glass systems can also be deposited by CVD methods using appropriate silicon, boron, and phosphorus precursors in an oxidizing environment.

A key technological implication of this compositional modification is the ability of these glass films to soften and flow during thermal treatment. In IC fabrication, this behavior has been exploited to address one of the major challenges in device manufacturing, namely, the planarization of surface topography prior to the formation of the metallization system. The use of flowing glass films enables the smoothing of surface irregularities in pre-metal dielectric (PMD) layers, thereby improving the reliability of subsequent metallization processes.

With the continued scaling and increasing complexity of IC technologies, further reductions in thermal processing temperatures became necessary, particularly after the formation of transistor structures. For example, in radiation-hardened ICs and silicon-on-sapphire devices developed in the early 1980s, post-transistor processing temperatures were required to remain below approximately 850 ℃ [4]. The introduction of BPSG materials made it possible to further reduce both T$_{\text{g}}$ and the corresponding flow temperature (T$_{\text{flow}}$). Experimental studies have shown that the temperature interval between T$_{\text{g}}$ and T$_{\text{flow}}$ for BPSG compositions is approximately 288 ℃ with a standard deviation of 16 ℃. As a result, BPSG thin films capable of flowing at temperatures above approximately 700 ℃ after CVD deposition have been widely adopted [5].

Low-temperature flowable BPSG films have been used as PMD materials in IC technologies since the 1980s, covering technology nodes from approximately 3 $\mu$m down to 180 nm, corresponding to multiple generations of device development. Over this period, extensive experimental work has been carried out on BPSG films, including studies of deposition methods, growth kinetics, composition control, structural characteristics, defect formation, and process performance. The accumulated results have been reported in numerous publications [6], [7], [8] and summarized in a monograph [9]. These studies provide detailed descriptions of CVD processes, film properties, and the effectiveness of glass flow in addressing planarization and defect-related issues in IC fabrication. A notable feature of CVD-deposited glass films is the formation of a fully developed glass structure at temperatures significantly lower than the glass transition temperature associated with conventional bulk glass synthesis [9].

In addition to their established role in IC technologies, BPSG films have also attracted attention for applications in other device systems. In recent years, previously unavailable experimental data have become accessible in digitized form, providing further insight into BPSG film behaviour. At the same time, certain properties that are not directly relevant to IC fabrication, such as optical characteristics, have been explored for applications in optical devices and microsystem technologies (MST). In these contexts, alternative deposition approaches, such as spin-on methods followed by thermal treatment, have also been considered.

The development of IC fabrication technologies has enabled the creation of a wide range of miniature MST devices, including micro-electro-mechanical systems (MEMS), micro-electro-optical-mechanical systems (MOEMS), and integrated optical components. The ability of BPSG films to undergo controlled flow has been applied not only to planarization but also to the formation of specific structural features, such as cavities, channels, and functional geometries in these systems. These applications suggest that the effects associated with low-temperature glass softening and flow may be utilized for a broader range of engineering functions beyond their original role in IC processing.

Despite the extensive body of experimental work and the diversity of applications, existing studies have largely addressed BPSG films within specific technological contexts. A consistent interpretation of the underlying physical behaviour, particularly in relation to the interaction between composition, thermal processing, and structural evolution across different device systems, remains limited. In this context, a systematic examination of the behaviour of CVD BPSG films across IC, MST, and optical applications is of interest.

In the present study, the available data on CVD BPSG films up to 2025 are examined with the aim of clarifying their behaviour and application characteristics across different technological domains. The discussion includes their use in IC fabrication, followed by their implementation in MST and optical device technologies.

The creation of IC device elements (transistors, capacitors, resistors is carried out according to so-called technological process flows. They include up to several hundred different technological operations of application of dielectric, conductive, semiconductor, and metal layers, their etching, photolithography, ion implantation, firing, etc. IC technologies are implemented based on a so-called planar manufacturing approach [10]. According to it, the creation of device elements is carried out in/on the original substrate in one plane consecutively in a downward-upward direction, layer by layer of a certain small thickness. In IC technologies, certain local areas of conductivity or insulation are first created in the surface area of the substrate. The substrate surface must then be treated with a variety of inorganic materials. Since the use of bulk materials is not possible with a planar approach, it becomes necessary to create materials in the form of thin films, usually of a thickness of micrometers or less. On the surface of these films by photolithography processes create the necessary drawings, according to which further defined areas of thin film are removed by liquid, gas, or plasma etching. Eventually, the elements of the device structures of a certain shape are formed, for example, IC transistor structures.

Modern ICs are extremely complex and contain dozens of different materials and layers. However, any complexity of the IC structure can be conveniently presented as a simplified cross-sectional block scheme, Figure 1. In this scheme, the IC structure is shown as several major blocks starting from the substrate up. The technological sub-process flow for creating transistor structures in/on substrate 1 (indicated as blocks 2—diffusion/insulating regions in the near-surface substrate regions, and block 3—a region of transistor structures laterally isolated from each other) is called “Front End of Line” (FEOL). Chronologically, it is for the FEOL area that there is a tendency to reduce the size of transistors according to Moore’s Law. The completion of the FEOL sub-process flow is the creation on top of transistor structures of a continuous insulating layer of PMD, Figure 1. In the PMD layer, through-holes are etched to the transistor structures on the substrate, called contact windows.

The subsequent sub-process flow for forming a multilevel metallization system (block number 4 in Figure 1) is called “Back End of Line” (BEOL), First, in the contact windows, metallic conductive elements are created, i.e., metal contacts to the transistors, to the substrate, etc. After that, a system of metal conductors is formed, isolated from each other by so-called Inter Metal Dielectrics. IC manufacturing is completing with final IC passivation with etched windows in dielectrics to open metallic contact areas (block number 5 in Figure 1). Chronologically, trends of changes in the BEOL consist of increasing the number of metallization layers to organize the connections of the increasing number of transistors in the FEOL.

The reliability of the BEOL metallization system is directly determined by the planarity of the PMD. Historically, three main problems were faced and solved.

The problem was first identified at the end of the 1970s–1980s. Its essence consists of toning and breaking the continuity of metallic conductors of sub-process flow BEOL when they are created on an uneven surface PMD. A scheme in Figure 2a shows that the thickness of the conductor in the lower corners of the relief can be several times less than its thickness over the elements of the relief. The example Scanning Electron Microscopy (SEM) photo in Figure 2b shows film drowning in the metal line bottom. This type of coating is referred to as non-conformal (that is, uneven in thickness on different elements of the relief), see Figure 3a. The reason for non-conformality is the directionality of the sputtering of the aluminum. In this case, non-conformal coatings are formed on the vertical steps of any IC relief and in the contact windows, as shown in Figure 3a and Figure 3b. The conformality value (ratio d$_2$/d$_1$, %) can range from a few tenths of a percent to a complete lack of material in the lower corners of the relief. In the case of metallic conductors, this means that the resistance of the conductors is impaired until they break. To solve the problem, it is necessary to level the PMD surface. It turned out to be possible by using the property of glass flow on the IC relief when heating thin PSG and BPSG films, Figure 4a and Figure 4b.

Using photolithography and etching methods, the holes in PMD are formed for contacts of metal conductors to the transistors and other devices. Isotropic liquid etching techniques allowed us to obtain a tapered shape of a contact hole in the cross-section, Figure 5a. This form of contact holes did not cause problems with metallization. However, the shrinking of the IC technology node led to a change in the shape of the contact windows to cylindrical in section, Figure 5b. This is done by plasma etching. The problem in this case is similar to the previous one and consists of the non-conformality of the sputtered aluminum, similar to that shown in Figure 2.

The problem lies in the formation of voids within the IC relief due to non-conformal CVD of thin films, see Figure 3a. This problem (commonly known as “voids” and “gap-fill”, see Figure 3b, has become more prominent when the IC technology node was reduced to less than 500 nm in size. Voids inside the relief are not acceptable because they cause problems of etching uniformity and can be filled with liquid reagents during IC manufacturing. The problem of voids is reinforced for structures with high aspect ratio gaps, see Figure 3c.

The use of the phenomenon of the flow of glass allowed us to solve one of the most serious IC technology problems, namely, surface planarization with glass dielectric material before the formation of the IC metallization system [11]. PSG films containing about 10 wt \% of phosphorus were produced by CVD methods using, for example, silane and phosphine PH3 with oxygen [12-13]. The film of a certain composition was grown in industrial CVD equipment on substrates with IC structures. The films were then thermally treated at temperatures above 1000–1100 °C in oxygen, argon, or nitrogen for several tens of minutes. Typically, this was done in diffusion furnaces with hot-wall tubular quartz reactors. The heating caused softening and flowing of the glass, smoothing the roughness of the relief as shown in Figure 4a and b. A few years later, further development of IC technologies required a significant reduction in processing temperature after the formation of transistor structures. Thanks to this strong requirement [4-5], BPSG films have replaced PSG films on several generations of ICs, including commercial ICs. Need to note that there are about 10 known methods for BPSG thin film deposition, and their detailed description and analysis can be found in study [9].

Figure 6a-- Figure 6d show SEM images of IC elements with BPSG films for all the above-mentioned technology problems. On the left are the images after BPSG film deposition. On the right are the same elements after heat treatment that caused glass flow. It can be seen in Figure 6a and Figure 6b that the softening of glass on the relief (flow process) leads to smoothing irregularities. The following second heating (usually named “reflow”) leads to smoothing of the upper edges of the contact holes, see Figure 6c and Figure 6d. Note that this issue was later solved in another way. Contact to the silicon substrate in the vertical window was formed using a unique technology of selective metal tungsten deposition in the direction from the surface of the silicon up (named as tungsten-plug technology). The softening/flow of glass when heated also leads to a reduction/disappearance of voids in the relief, as shown in Figure 6e and Figure 6f. This is the case of heavily heated glass films. However, in case of non-sufficient heat impact, the glass flow effectiveness slows down and key-hole shaped voids transform into small round voids, Figure 6g.

BPSG technology with planarization by glass film flow is used in IC technologies down to approximately 350 nm technology nodes. The planarization efficiency (i.e., the degree of reduction in the height of the irregularities of the relief after the glass flow) and gap-fill depended on the concentrations of boron [B], phosphorus [P], anneal temperature (T, °C), and heating time (t) of the glass, and on the thin film conformality on the relief (d2/d1). The latter was largely initiating the new glass CVD production techniques using ozone as an oxidant. Attempts to quantify the multifactorial effectiveness of planarization were systematized in study [9]. The impact of film characteristics and heat treatment on the resolution of PMD problems is shown in Table 1.

It should be noted that the use of flow-able glass technology occurred in parallel with the search for other promising methods for improving the planarization of PMD while reducing the overall thermal impact on ICs. For example, the authors [14] compared three technological methods: BPSG flowing at elevated pressure, sequential film deposition-etching-deposition sequence (known as the Etch-Back process), and the use of spin-on-glass dielectrics. Increasing the flow pressure to 25 atmospheres made it possible to achieve improved planarization at a temperature of 800 °C and 30 minutes in nitrogen, oxygen, or steam ambient. But the equipment involved was quite complex, and the use of oxygen/steam ambient required a thick enough liner to prevent oxidation under BPSG film. The latter affected PMD gap-fill.

To improve the limited lithography depth-of-focus and increase the yield of metal interconnect, PMD BPSG film global planarization across the whole IC chips is used in ICs with technology nodes 350 nm and below. Chemical Mechanical Polishing technology is the only technology to achieve global planarization, including PMD. For this purpose, thicker BPSG films are implemented. This ensured a sufficient thickness of the dielectric after removing the upper uneven part of the glass, Figure 4c and Figure 4d. In this case, the need for high-temperature furnace heating to smooth the relief surface using glass flow ability is no longer relevant. However, BPSG thermal treatments have been preserved and used to solve the problems of eliminating voids in IC gaps with glass and film densification. In this case, the BPSG thermal treatment is used at lower temperatures, for example, at 750 ℃. Rapid Thermal Anneal (RTA) is also used in this step to reduce the total thermal budget on the ICs. In some cases, such conditions are not sufficient for proper softening of the glass; it is necessary to optimize the RTA conditions to remove the voids inside the relief.

Oxide materials like silicate glass films are polished using alkaline solutions. It was found that the polishing rate increases with both boron and phosphorus concentrations in BPSG films. The phosphorus was found to have a slightly stronger effect on the polishing rate than boron. An example of the polishing rate of BPSG film as a function of total boron and phosphorus content is shown in Figure 7 [9]. The polishing rate increases almost linearly with total boron and phosphorus concentration in the range of concentration studied. A possible mechanism for the increasing polishing rate with additive concentration assumes the difference in additive structures with respect to the silica structure. Additives weaken the structure of the oxide network with the increase of the additive content. Weakening the structure of oxide films may allow the additive oxide to dissolve faster in the high pH silica slurry and therefore result in a higher polishing rate.

A few other applications of BPSG films have been discussed in the literature.

i) Kondo et al. [15] showed the use of BPSG films in the FEOL sub-process flow as an insulation dielectric in trenches etched in silicon, as shown in the simplified diagrams in Figure 8. Here, CVD BPSG film with flow was used to fill the trenches in silicon substrates with a width of 0.8 $\mu$m. After that, excessive material on top of the structures was removed using etch-back plasma etching. It should be noted that silicon dioxide is mainly used for trench isolation in IC technologies, and CMP is used to align it flush with the substrate surface.

ii) It should be noted that modern integrated technologies largely rely on and borrow technological processes from rapidly developing industrial IC technologies and, above all, Complementary Metal Oxide Semiconductor (CMOS) IC technologies. However, in addition to the already largely standardized applications, some types of integrated technologies imply their own manufacturing process flows. For example, there is a wide variety of devices grouped under the general term MEMS or MOEMS. These devices use other characteristics of thin films, like the dissolution rates in liquid etchants, the refractive indices of thin films, and the possibility of their variation, etc. However, there are also options for combining CMOS ICs and MEMS technologies in one process flow CMOS. The reviews [16], [17] provide some examples of CMOS-integrated IC – MEMS devices formed by etching the deep cavities in silicon to produce, for instance, sensitive membranes. The author of the review [16] selected three types of CMOS-MEMS combination technology depending on what is supposed to be realized first: pre-CMOS MEMS, inter-CMOS-MEMS, or post-CMOS MEMS. A simplified scheme of a pre-CMOS MEMS device structure is shown in Figure 9. One can see that this recessed structure is formed first, followed by filling with a sacrificial material (including glass materials) to make the surface globally flat. After that, the CMOS device is formed according to its process flow. Finally, the sacrificial layer is removed by wet etch.

iii) The passivating coating for IC is the last material of the BEOL sub-process flow, separating the IC chips from the environment, as indicated by number 5 in the scheme in Figure 1. CVD PSG films were traditionally used as such a material [18]. The main functions of the material are the protection of metallization and the gettering (retention in its thickness) of alkali metal ions. Sufficiently thick films are used to comply with the first function. Their mechanical stresses must be balanced with aluminum metallization to avoid cracking of the protective coating. BPSG films have also been studied for use as passivating coatings. The BPSG films showed suitable values of mechanical stresses and gettering properties. However, the effects of the interaction of BPSG films with ambient moisture [9] are obviously negative for ICs. Moreover, in this case, the films are used in the as-deposited version and can be in contact with air for a long time, with the corresponding consequences. As a result of studies, a combination of low-temperature PSG (gettering film) and low-temperature plasma-enhanced deposited silicon nitride SiN$_{{\text{x}}}$ (hydrophobic film) was chosen to protect the ICs, as shown in Figure 1.

Summing up this section, the author would like to note the following. Some digital versions of early publications, mainly proceedings of the conference, concerned the effectiveness of BPSG film flowing on IC device reliefs. They include mainly results of multifactorial planarization evaluations of the dependence of the angle of inclination of the flowed glass on the top of different IC reliefs on the concentrations of additives and the conditions of glass annealing, namely: heating method, temperature, time, and the annealing ambient. The data presented in these publications were consistent with previously made generalizations, and therefore, there was no need to include them in this overview. It would not be contradictory to consider that the generalizations given in the monograph [9] adequately outline the scope of using CVD BPSG films in IC technologies. Indeed, the generalizations include a number of CVD methods for obtaining films, film properties, quantitative ranges of optimal compositions for required glass film flow and planarization, as well as ensuring their defect-free nature. As for recent publications related to the use of CVD BPSG in semiconductor technologies, they are mainly related to the optimization of thermal treatments of PMD films. For example, they consider the issues of reducing and optimizing the level of thermal budget on glass films [19], [20] and optimizing the mechanical stresses in BPSG films in some devices [21], [22]. Recent applications of films in ICs and semiconductor devices have also been reported [23], [24].

MEMS technologies are largely based on IC technologies and processes. However, there are several design features that require different processes and materials with different properties. A few fundamentally different structural elements of MEMS can be distinguished as follows: membranes/diaphragms, trenches or cavities of various shapes and sizes, and “suspended” elements above the cavities, fixed on one or two ends. Such designs can be implemented with the help of two fundamental technological features. To form large and deep cavities in the silicon substrate, etching processes are required either in liquid anisotropic etchants or using deep reactive ion etching (DRIE). After that, cavities are temporarily filled with “sacrificed” layers of materials with very high selective etching rates. The following step is to create a suspended element over these sacrificial materials, and then to remove the sacrificial layer by etching to release the suspended element.

For example, the use of BPSG film as a sacrificial material with a thickness of 0.9 and 1.8 $\mu$m in the production of a piezoresistive microcantilever is described in study [25]. This paper is devoted to the design and fabrication of a piezoresistive microcantilever sensor as a platform for biological sensing, such as salivary amylase activity for human stress measurement applications. The etchants used for BPSG removal were pure hydrofluoric acid, HF (49%), 10:1 Buffered Oxide Etch, and ammoniumfluoride–based acid. Another recent example of BPSG film implementation as a sacrificial material can be found in study [26].

Let's look at some examples of CVD BPSG film implementation in MEMS technologies. Examples of the use of BPSG films in devices below are illustrated with simplified drawings. SEM photos of the corresponding structures can be found in the cited references.

i) Anisotropic etching of shallow trenches in silicon is carried out in potassium hydroxide (KOH) solution. In this case, the side walls of the recess may have various types of irregularities. For some devices, such irregularities are unacceptable. French and Wolffenbuttel [27] used the flow effect of a one micron thick BPSG film at 950 ℃ for 45 minutes to smooth out the sidewall irregularities. A simplified scheme of such a technique is shown in Figure 10a. This made it possible to eliminate irregularities on the side walls of the etched cavity. The alignment (planarization) of the ripple surface of the side walls in deep trenches etched using DRIE technologies is described by Weng et al. [28]. The profile scheme of such a trench is shown in Figure 10b. Applying a thin layer of BPSG followed by glass flow made it possible to level the surface. The effect of surface tension forces in BPSG films during their softening and flow was used in both these examples. The base of this solution seems to be glass film smoothening at the flow on the IC device relief, see example in Figure 6a and Figure 6b.

ii) Another application of BPSG films using deep anisotropic etching of silicon is described in study [29]. The as-deposited BPSG films were studied as a protective mask during wet-etching of silicon substrates in KOH solution within 4 hours at 85 ℃. The composition of 11 wt \% B and 4 wt \% P was chosen as the lowest in terms of dissolution rate and mechanical stresses, allowing the application of thick films compatible with aluminum metallization. This etching technique can be used, for instance, as part of the above-described combination of ICs and MEMS named post-CMOS MEMS. However, in addition to the thick BPSG film, a CVD SiO$_2$ film was applied above and below to avoid contamination of the substrate with boron and phosphorus and to prevent the film from contacting the ambient. It can additionally be noted here that any BPSG films have revealed interesting wet etching dependencies [9]: in diluted HF, the etching rates increase linearly with phosphorus concentration, see Figure 11a. However, in buffered HF, the etching rates of BPSG films decrease by 3–5 times with increasing boron concentration, Figure 11b. These effects were used for a very rough, but very quick evaluation of additive content in the as-deposited BPSG films.

iii) Rusu et al. [30] showed the effects of BPSG softening to form isolated sealed cavities in MEMS devices. The device gaps were about 2–3 $\mu$m in width and about 9–10 $\mu$m in height. The feature of extremely non-conformal Plasma-Enhanced Chemical Vapor Deposition (PECVD) films on reliefs was used. Plasma-activated thin film deposition allows us to obtain device elements with overhang film profiles, see Figure 12a. Need to note that such profiles are not acceptable in IC technologies with technology nodes below 500 nm. However, in this case, PECVD films are preferable. When the glass films are heated and melt, the overhanging parts of the films on neighboring elements fuse, Figure 12a, eventually forming a cap above the cavity, Figure 12b.

A similar idea is used to form longitudinal channels between the relief elements of the microfluidic MEMS devices [31]. The main reason for this solution seems to be the observed effect of changing the shape of the voids in the IC relief from triangular to rounded, Figure 6g. In this case, triangular-shaped voids in the relief covered with extremely non-conformal PECVD BPSG films, Figure 13a, turn into rounded ones after glass melting, see Figure 13b. The size of the circular voids is determined by the ratio of the relief dimensions, the thickness and composition of the film, and the conditions of its heat treatment. It should be noted that PECVD films are more convenient for forming channels of the desired size. However, this effect also occurs for initially highly conformal films, such as so-called “TEOS-ozone SACVD BPSG films” [9]. It can be seen in Figure 6g that insufficiently effective melting, such as in the case of RTA, causes small triangular voids to transform into small rounded voids. However, initially highly non-conformal film deposition allows for greater control over channel size. Thus, cavities of various shapes, sizes, and lengths can be formed in the devices at relatively low melting temperatures of the BPSG. Particularly, these approaches have been demonstrated for microfluidic device designing as a part of Lab-on-Chip devices [32]. A couple of recent examples of microfluidic devices with the application of BPSG films can be found in study [33], [34].

iv) The idea of changing the inclination of the side walls of the hole, see Figure 6c and Figure 6d, was used to manufacture a matrix for forming the metal tip of field emitter arrays of vacuum transistors [35]. The presented process flow includes a number of CVD films used in CMOS ICs: silicon dioxide, polysilicon, BPSG, and titanium nitride (TiN). The simplified sequence of the tip manufacturing with CVD and etched films is shown in Figure 14(a–e). As can be seen, the main feature of the tip sharpening is the BPSG film flow with smooth sidewalls. Following CVD silicon dioxide deposition allows one to make a precise tip form.

From the data presented, it can be seen that the main characteristic of BPSG films used is their ability to melt at low temperatures.

Let us consider two areas of application of CVD BPSG films in integrated optical devices: i) the manufacture of microlenses and actuators from transparent films, and ii) the use of the films as a cladding material for waveguides in planar optical lightwave circuits.

i) Tsukamoto et al. [36] proposed a new technology for creating highly sensitive pixels for an Inter-line Transfer Charge Coupled Device using BPSG film. The flowed transparent BPSG film served as the lower part of the composite lens system formed above the photodiode manufactured in the substrate. In the traditional implementation of the device, an aluminum layer, a passivating dielectric layer, and polymer materials for composite lenses were used to form a window above the photodiode. The replacement of aluminum with tungsten silicide made it possible to increase the temperature of lens formation. The lower part of the composite lens was created from a flowed BPSG, Figure 15. This technique significantly improved the focusing of light and reduced the pixel size. The described option allows us to create a passive lens from the BPSG film. Henriksen et al. [37] and Costantini et al. [38] described the use of very thick transparent BPSG film as a part of a thin film piezoelectric actuator in a MOEMS device that changes bending when voltage is applied, Figure 16. Changing the bend made it possible to quickly control the change in focal length. The main difference of this technology is the use of very thick (about 20 microns) BPSG films and a control piezoelectric electrode on its surface. Obviously, using such a thick film is necessary to provide its transparency, long-term stability, i.e., glass film homogeneity. BPSG films were carefully optimized in composition. They were also deposited and thermally treated in several steps to avoid mechanical stresses. A detailed review of the results of mechanical stress measurements in CVD glass films is given in study [39]. In particular, we note that the sign and magnitude of mechanical stresses in CVD glass films strongly depend on both the CVD production method and the composition of the films. In addition, post-deposition thermal treatment of glass films also leads to a change in stress values. All this makes it possible to control the values of mechanical stresses, which is especially important for thick glass films. It is very important to highlight that in both considered cases, the film must be transparent without any solid/crystal defects inside.

ii) In the previous studies [40], [41], [42], [43], [44], [45], various techniques are discussed for using CVD BPSG films as a cladding material for planar optical waveguides formed, for example, on silicon substrates. Figure 17 shows a simplified cross-section scheme for using flowed thick BPSG films. In this case, the point of using BPSG films is that by changing the content of additives, the refractive index of the films can be changed. In fact, the first review published in 1988 allowed the authors to conclude that refractive index depends on phosphorus concentration in PSG and BPSG films in the range of 1,44–1,47 [9]. Evaluation of refractive index in annealed BPSG films gave the number of 0.0016 per one wt % of phosphorus [46]. This allows us to use this film as a lower refractive index than that of the waveguide material. For instance, silicon oxynitride (SiON) materials can have refractive index values in the range of 1.5–2.0, which allows for maximum internal reflection and low losses of the light beam. Some comparative optical-related data on different CVD films can be found in study [44], [45].

Note that this direction of BPSG films also implies a high film thickness. The use of CVD films in this case is very expensive. In the early 1990s, a significantly cheaper method for producing BPSG was proposed and developed. It is known as the so-called sol-gel method [47], [48]. Films of the required composition are prepared by mixing the initial reagents in the liquid phase and then undergoing a series of treatments and annealing. Syms et al. [48] showed that sol-gel BPSG films revealed the positive refractive index trend for phosphorus with a number of 0.0010 per one wt % of phosphorus, but a negative trend for boron with a number of about 0.0044 per one wt % of boron. A detailed description of the manufacturing technology is given in study [48]. This method is compatible with integrated IC technologies on semiconductor substrates, known as spin-on. However, it is outside the scope of this overview at this moment.

It can be seen that, besides the main characteristic of BPSG films (their ability to melt at low temperatures), the other properties can also be used.

CVD BPSG thin films enable the formation of glass structures through low-temperature manufacturing processes at temperatures significantly below the glass transition temperature (T$_{\text{g}}$) of equivalent compositions produced by conventional sintering methods. This capability underlies their long-standing use as PMD materials in IC technologies, covering technology nodes from approximately 3.0 $\mu$m down to 180 nm. In the development of multilevel metallization systems, two principal technological approaches have been employed. The first involves thermal treatment of BPSG films to induce softening and viscous flow, allowing the material to conform to the underlying device topography and achieve local surface planarization. The second approach relies on film densification at temperatures sufficient to eliminate voids within the device relief, followed by Chemical Mechanical Polishing to achieve global planarization.

The effectiveness of these approaches depends on a combination of factors, including film composition, deposition conditions, and thermal treatment parameters. In particular, the incorporation of boron and phosphorus oxides modifies the glass transition behaviour and enables controlled flow at reduced temperatures, while also influencing defect formation, stress evolution, and planarization efficiency. Optimization of BPSG-based PMD technologies therefore requires coordinated control of material composition, process conditions, and equipment selection, together with careful management of defect formation during deposition and reflow stages. Experimental studies reported in the literature, including early and more recent works, provide consistent observations of these dependencies and offer a basis for further refinement of processing strategies.

Beyond IC technologies, CVD BPSG films have been successfully applied in MEMS and optical device fabrication. In these systems, the same fundamental behaviour—thermally activated softening and flow–enables additional functionalities, such as the formation of cavities, channels, and complex geometries in MEMS, as well as the realization of optical components including microlenses, actuators, and waveguide cladding layers. In these applications, the performance of BPSG films is not determined solely by their ability to flow, but also by their chemical stability, mechanical properties, and optical characteristics. Compared to IC applications, these systems often require significantly thicker films, which introduces additional constraints related to stress control, deposition uniformity, and thermal treatment conditions. In optical applications in particular, the transparency of the films and the absence of structural defects become critical factors.

A defining characteristic of CVD glass thin films is the formation of a fully developed glass structure at synthesis temperatures well below the glass transition temperature of corresponding bulk materials. Combined with the high uniformity of composition and the capability to produce films of substantial thickness on large substrates, this feature enables the realization of reliable and high-quality glass-based structures. For applications requiring precise control of geometry and material properties, CVD-based approaches remain a preferred solution, although they are associated with higher process complexity and cost.

At the same time, alternative methods such as sol-gel processing provide a lower-cost route to the production of boron- and phosphorus-containing glass materials. In contrast to CVD processes, the glass structure in sol-gel systems is formed during subsequent thermal treatments, and the classical T$_{\text{g}}$ concept applies directly. While such approaches offer advantages in simplicity and cost, they require detailed materials characterization across the full processing cycle to ensure performance comparable to CVD films. The further development and application of these alternative technologies remain an open area for future investigation.

Overall, the behaviour and functionality of BPSG thin films can be understood in terms of the interaction between thermal activation, material composition, and geometrical constraints. This interaction governs not only the flow characteristics of the films, but also their role in determining structural evolution, defect formation, and device performance across different technological domains. A consistent understanding of these relationships provides a basis for the rational design and optimization of processes involving BPSG films in integrated and MST. Further work may focus on establishing quantitative relationships between thermal flow behaviour and device-scale performance to support process optimisation under practical manufacturing conditions.